We provide coverage-driven functional verification services for Digital Design, from block-level to system-level and gate-level, by mixing software and programming skills with hardware and digital circuits knowledge
More than ever, the major tech innovators want to map out their own futures via innovative chip development, instead of trying to adapt existing infrastructure and hardware to new and unforeseen purposes. However, with great innovation comes the need for an assiduous attention to detail, and a pioneering attitude rare to most tech work-spaces .
Three phases to market
The chip development workflow can be roughly divided into 3 main phases:
- System Level Design - where the architects map out the chips’ functionality
- Registered Transfer Level (RTL) design - where a software simulation of the chip is used to evaluate its viability
- Physical Design - where the first prototype is produced
Functional verification is applied to the chip development workflow throughout the second stage, all the way to ‘tape out’, from which a real-world chip will be produced for advanced testing.
However, the verification team is also likely to work with the architects at the initial stage, to ensure no obvious potential failings are designed into the concept chip.
Tremend works with a variety of technologies and systems for Chip Design Verification, including Cadence Incisive Enterprise Simulator, Synopsys VCS and Verdi, Mentor Questa Verification Solution, e-Language, System Verilog, UVM and eRM.
Our engineers in the Chip Design Verification department are always up to date with the latest developments in the industry and have developed their area of creativity and lateral thinking, along with a logical and analytical mind.